C_CPE_15 Practice Questions

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NEW QUESTION: 1
A physician excises a 3.1-cm malignant lesion of the scalp that requires full-thickness graft from the thigh to the scalp. In CPT, which of the following procedures should be coded?
A. full-thickness skin graft to scalp only
B. code 15000 for surgical preparation of recipient site; full-thickness skin graft to scalp
C. excision of lesion; full-thickness skin graft to scalp; excision of skin from thigh
D. excision of lesion; full-thickness skin graft to scalp
Answer: D

NEW QUESTION: 2
Where can a Citrix Administrator activate XML Service Trust in XenDesktop?
A. StoreFront
B. Citrix Studio
C. Group Policy
D. PowerShell
Answer: C

NEW QUESTION: 3
A network administrator is expanding a network from one host to 300 hosts. The network must be configured to use only the company's single public IP address. Which of the following configurations would be BEST suited for this task? (Select TWO).
A. Enable NAT on the router and request an IPv6 address from the ISP.
B. Use the network ID and mask 192.168.0.0/24.
C. Enable NAT with port address translation on the router.
D. Enable NAT on the router and request a block of five IP addresses from the ISP.
E. Use the network ID and mask 192.168.0.0/23.
F. Use the network ID and mask 192.168.0.0/25.
Answer: A,F

NEW QUESTION: 4
What is the name of the core-to-core transport mechanism used in Intel XEON processors?
A. Northbridge
B. Crossbar switch
C. Quick Path Interconnect
D. Hyper Transport
Answer: C
Explanation:
The way I understand it, Crossbar is not a technology name, but a switch that assist in communication between processors, memory etc, allowing inter core & inter CPU communication. QPI, FSB & HT are all types of connections, connected to crossbar switches. All the answers are connected to crossbards, but only Intel has QPI. I would still go with QPI
www.site.uottawa.ca/~mbolic/ceg4131/Report Crossbar switches.pdf
A. Intel Xeon 7500 architecture The Intel Xeon 7500 series processor architectures uses an 8 port crossbar switch which implements the Intel QuickPath Interconnect (QPI) and routing layers. The Intel QPI is point-point interconnection link developed by Intel [1] to compete with HyperTransport. Prior to using QPI the Intel architecture was using the Front Side Bus (FSB) [2] which was the bus that carried data between CPU and the memory controller (northbridge) and I/O controller(southbridge).
The off-chip single memory controller often was the bottleneck which prevented faster CPUs from improving the overall performance of the system. Now, with crossbar implementation the microprocessor were able to integrate the northbridge on-chip for faster access As well: (Thanx MaaShar from Belgium)
http://www.intel.com/content/www/us/en/io/quickpath-technology/quickpath-technology- general.html
Intel@ QuickPath Technology uses Intel@ QuickPath Interconnect, which provides high-speed, point-to-point links inside and outside of the processor. In contrast to parallel buses, these links speed up data transfers by connecting distributed shared memory, the internal cores, the I/O hub, and other Intel@ processors.